(1PC) ISPLSI5512V110LB388 Lattice EE PLD, 10ns, 512-Cell, CMOS, PBGA388
Tax included.
This listing is for (1PC) of ISPLSI5512V110LB388 by Lattice
Mfr Package Description BGA-388
REACH Compliant Yes
Status Discontinued
Programmable Logic Type EE PLD
Clock Frequency-Max 80.0 MHz
In-System Programmable YES
JESD-30 Code S-PBGA-B388
JESD-609 Code e0
JTAG BST YES
Moisture Sensitivity Level 3
Number of Dedicated Inputs 0.0
Number of I/O Lines 288.0
Number of Macro Cells 512.0
Number of Terminals 388
Operating Temperature-Min 0.0 Cel
Operating Temperature-Max 70.0 Cel
Organization 0 DEDICATED INPUTS, 288 I/O
Output Function MACROCELL
Package Body Material PLASTIC/EPOXY
Package Code BGA
Package Equivalence Code BGA388,26X26,50
Package Shape SQUARE
Package Style GRID ARRAY
Peak Reflow Temperature (Cel) 225
Power Supplies 2.5/3.3,3.3
Propagation Delay 10.0 ns
Qualification Status Not Qualified
Seated Height-Max 3.25 mm
Sub Category Programmable Logic Devices
Supply Voltage-Nom 3.3 V
Supply Voltage-Min 3.0 V
Supply Voltage-Max 3.6 V
Surface Mount YES
Technology CMOS
Temperature Grade COMMERCIAL
Terminal Finish TIN LEAD
Terminal Form BALL
Terminal Pitch 1.27 mm
Terminal Position BOTTOM
Time@Peak Reflow Temperature-Max (s) 30
Length 35.0 mm
Width 35.0 mm