(1PC) GAL6002B-15LP EE PLD, 15ns, PLS-Type, CMOS, PDIP24
Tax included.
This listing is for (1PC) of GAL6002B-15LP by Lattice
Status Discontinued
Programmable Logic Type EE PLD
Architecture PLS-TYPE
Clock Frequency-Max 43.4 MHz
JESD-30 Code R-PDIP-T24
JESD-609 Code e0
Number of Dedicated Inputs 10.0
Number of I/O Lines 10.0
Number of Inputs 20.0
Number of Outputs 10.0
Number of Product Terms 75.0
Number of Terminals 24
Operating Temperature-Min 0.0 Cel
Operating Temperature-Max 75.0 Cel
Organization 10 DEDICATED INPUTS, 10 I/O
Output Function MACROCELL
Package Body Material PLASTIC/EPOXY
Package Code DIP
Package Equivalence Code DIP24,.3
Package Shape RECTANGULAR
Package Style IN-LINE
Power Supplies 5
Propagation Delay 15.0 ns
Qualification Status Not Qualified
Seated Height-Max 4.57 mm
Sub Category Programmable Logic Devices
Supply Voltage-Nom 5.0 V
Supply Voltage-Min 4.75 V
Supply Voltage-Max 5.25 V
Surface Mount NO
Technology CMOS
Temperature Grade COMMERCIAL EXTENDED
Terminal Finish Tin/Lead (Sn85Pb15)
Terminal Form THROUGH-HOLE
Terminal Pitch 2.54 mm
Terminal Position DUAL
Length 31.855 mm
Width 7.62 mm
Additional Feature REGISTER PRELOAD; POWER-UP RESET