(1PC) EPM7128SQC100-10 Altera CPLD 2.5K Gates 128 Macro 100MHz CMOS 5V QFP100
Tax included.
This listing is for (1PC) of EPM7128SQC100-10 by Altera
Status Transferred
Additional Feature CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V
Clock Frequency-Max (MHz) 125.00000
In-System Programmable YES
JESD-30 Code R-PQFP-G100
J-STD-609 Code e0
JTAG BST YES
Length (mm) 20.0000
Moisture Sensitivity Level 3
Number of Dedicated Inputs 0
Number of I/O Lines 84
Number of Macro Cells 128
Number of Terminals 100
Operating Temperature-Max (Cel) 70.0
Operating Temperature-Min (Cel) 0.0
Organization 0 DEDICATED INPUTS, 84 I/O
Output Function MACROCELL
Package Body Material PLASTIC/EPOXY
Package Code QFP
Package Equivalence Code QFP100,.7X.9
Package Shape RECTANGULAR
Package Style FLATPACK
Peak Reflow Temperature (Cel) 220
Programmable Logic Type EE PLD
Propagation Delay (ns) 10.000
DLA Qualification Not Qualified
Seated Height-Max (mm) 3.6500
Supply Voltage-Max (V) 5.25000
Supply Voltage-Min (V) 4.75000
Supply Voltage-Nom (V) 5
Surface Mount YES
Technology CMOS
Temperature Grade COMMERCIAL
Terminal Finish TIN LEAD
Terminal Form GULL WING
Terminal Pitch (mm) 0.650
Terminal Position QUAD
Time@Peak Reflow Temperature-Max (s) 20
Width (mm) 14.0000
