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(1PC) EP20K400EFC672-1X ALTERA FPGA-CPLD-APEX 20K 1664 Macros 488 IO PBGA672
(1PC) EP20K400EFC672-1X ALTERA FPGA-CPLD-APEX 20K 1664 Macros 488 IO PBGA672
(1PC) EP20K400EFC672-1X ALTERA FPGA-CPLD-APEX 20K 1664 Macros 488 IO PBGA672

(1PC) EP20K400EFC672-1X ALTERA FPGA-CPLD-APEX 20K 1664 Macros 488 IO PBGA672

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THIS LISTING IS FOR (1PC) OF EP20K400EFC672-1X BY ALTERA

SPECIFICATIONS

Mfr Package Description FINE LINE, BGA-672
Status Transferred
Programmable Logic Type LOADABLE PLD
Clock Frequency-Max 160.0  MHz
JESD-30 Code S-PBGA-B672
JESD-609 Code e0
Moisture Sensitivity Level 3
Number of Dedicated Inputs 4.0
Number of I/O Lines 488.0
Number of Inputs 480.0
Number of Logic Cells 16640.0
Number of Outputs 480.0
Number of Terminals 672
Operating Temperature-Min 0.0  Cel
Operating Temperature-Max 85.0  Cel
Organization 4 DEDICATED INPUTS, 488 I/O
Output Function MACROCELL
Package Body Material PLASTIC/EPOXY
Package Code BGA
Package Equivalence Code BGA672,26X26,40
Package Shape SQUARE
Package Style GRID ARRAY
Peak Reflow Temperature (Cel) 220
Power Supplies 1.8,1.8/3.3
Propagation Delay 1.57  ns
Qualification Status Not Qualified
Seated Height-Max 3.5  mm
Sub Category Field Programmable Gate Arrays
Supply Voltage-Nom 1.8  V
Supply Voltage-Min 1.71  V
Supply Voltage-Max 1.89  V
Surface Mount YES
Technology CMOS
Temperature Grade OTHER
Terminal Finish Tin/Lead (Sn63Pb37)
Terminal Form BALL
Terminal Pitch 1.0  mm
Terminal Position BOTTOM
Time@Peak Reflow Temperature-Max (s) 30
Length 27.0  mm
Width 27.0  mm