(1 PC) NTE4531B, ECG4531B, Integrated Circuit, CMOS-12-Bit Parity Tree

(1 PC) NTE4531B, ECG4531B, Integrated Circuit, CMOS-12-Bit Parity Tree

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The NTE4531B (16−Lead DIP) and NTE4531BT (SOIC−16) are 12−bit parity tree devices constructed with MOS P−Channel and N−Channel enhancement mode devices in a single monolithic structure. The circuit consists of 12 data−bit inputs (D0 thru D11), an even or odd parity selection input (W) and an output (Q). The parity selection input can be considered as an additional bit. Words of less than 13 bits can generate an even or odd parity output if the remaining inputs are selected to contain an even or odd number of ones, respectively. Words of greater than 12−bits can be accommodated by cascading other NTE4531B devices by using the W input. Applications include checking or including a redundant (parity) bit to a word for error detection/correction systems, controller for remote digital sensors or switches (digital event detection/correction), or as a multiple input summer without carries. 

  • Noise Immunity = 45% of VDD (Typ) 
  • Supply Voltage Range: 3Vdc to 18Vdc 
  • All Output Buffered 
  • Capable of Driving Two Low−Power TTL Loads, One Low−Power Schottky TTL Load or Two HTL Loads Over the Rated Temperature Range 
  • Quiescent Current = 5nA/Package (Typ) at 5Vdc 
  • Variable Word Length 
  • Diode Protection on All Inputs 

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