(1PC) EPM7128SLC84-10 CPLD MAX 2.5K Gates 128 Macro Cells 100MHz 5V PLCC84
Tax included.
This listing is for (1PC) of EPM7128SLC84-10 by Altera
Mfr Package Description PLASTIC, LCC-84
Status Transferred
Programmable Logic Type EE PLD
Clock Frequency-Max 125.0 MHz
In-System Programmable YES
JESD-30 Code S-PQCC-J84
JESD-609 Code e0
JTAG BST YES
Moisture Sensitivity Level 2
Number of Dedicated Inputs 0.0
Number of I/O Lines 68.0
Number of Macro Cells 128.0
Number of Terminals 84
Operating Temperature-Min 0.0 Cel
Operating Temperature-Max 70.0 Cel
Organization 0 DEDICATED INPUTS, 68 I/O
Output Function MACROCELL
Package Body Material PLASTIC/EPOXY
Package Code QCCJ
Package Equivalence Code LDCC84,1.2SQ
Package Shape SQUARE
Package Style CHIP CARRIER
Peak Reflow Temperature (Cel) 220
Power Supplies 3.3/5,5
Propagation Delay 10.0 ns
Qualification Status Not Qualified
Seated Height-Max 5.08 mm
Sub Category Programmable Logic Devices
Supply Voltage-Nom 5.0 V
Supply Voltage-Min 4.75 V
Supply Voltage-Max 5.25 V
Surface Mount YES
Technology CMOS
Temperature Grade COMMERCIAL
Terminal Finish TIN LEAD
Terminal Form J BEND
Terminal Pitch 1.27 mm
Terminal Position QUAD
Time@Peak Reflow Temperature-Max (s) 20
Length 29.3116 mm
Width 29.3116 mm
Additional Feature CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V